Flash memory is a non-volatile type of memory which can be rewritten and retain its data content without power. Flash and other types of electronic memory devices are constructed of memory cells that individually store and provide access to data. A typical memory cell stores a single binary piece of information referred to as a bit, which has one of two possible states. The cells are commonly organized into multiple cell units such as bytes having eight cells and words having sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells, sometimes referred to as programming the cells, where the data can then be retrieved in a read operation. In addition to programming and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is set to a known state. In typical single-bit flash devices, each cell has one of two possible data states, either a programmed state or an erased state, where the data states correspond to the two possible binary states of the corresponding bit (e.g., programmed state represents binary “0” and erased state represents binary “1”). More recently, cells structures have been developed that are capable of storing two physically separated bits. Other multi-bit structures have been proposed, in which different multi-bit data combinations are represented as electrically distinguishable programming levels in a given cell.
Conventional flash memory cells include a metal oxide semiconductor (MOS) device with a gate structure in which data may be retained in the form of trapped electrical charge. The erase, program, and read operations are commonly performed by application of appropriate voltages to certain terminals of the cell MOS device. In a program or erase operation, the voltages are applied so as to cause a charge to be stored in the memory cell or removed from the cell, thereby changing or setting a threshold voltage of the cell. In a read operation, appropriate voltages are applied to cause a cell current to flow, wherein the amount of such current is related to the threshold voltage state of the cell and is thus indicative of the value of the data stored in the cell.
Conventional single-bit flash memory cells are often formed as a “stacked gate” or “SONOS” cell types. Stacked gate cells include a transistor structure having a source, a drain, and a channel in a substrate or p-well thereof, as well as a stacked gate structure overlying the channel that includes a gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. A doped polysilicon control gate overlies the interpoly dielectric layer to complete the stacked gate structure. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Conventional SONOS type cells (e.g., silicon-oxide-nitride-oxide-silicon) also include an ONO structure formed over the substrate channel, with a control gate formed over the ONO structure, but without a floating gate.
A continuing trend in flash and other types of memory device designs is the reduction of device dimensions and feature spacings, referred to as scaling. Other design goals include reducing power consumption and operating voltages in flash memories, as well as reducing the time required to perform read, program, and erase operations. Data in flash memory arrays is accessed along bitlines, typically formed as implanted lines that operate as the cell source/drains. Memory access speeds and device power consumption are adversely affected by high bitline contact resistance. The bitline contact resistance is in part affected by the electrical connection between the implanted source/drain regions of the substrate and overlying interconnection (e.g., metalization structures), usually consisting of a conductive contact formed through an intervening dielectric material. As flash memory devices are scaled, however, it becomes more difficult to maintain low bitline contact resistance, particularly where memory array bitlines become very thin and are spaced more closely (e.g., scaled bitline widths and bitline pitch). Accordingly, there remains a need for improved flash memory device fabrication techniques by which low bitline contact resistance can be facilitated in scaled flash memory devices.